The present invention relates, in general, to semiconductor devices, and more particularly, to a novel lateral bipolar transistor and method of manufacture.
In the past, the semiconductor industry has employed various bipolar processing methods to produce lateral bipolar transistors. These lateral bipolar transistors generally are similar to standard vertical bipolar transistors which have a base electrode positioned between the transistor's emitter and collector electrodes. The configuration of these prior lateral, bipolar transistors generally results in a transistor that occupies a large area. The transistor's large size results in large spacings between the transistor's active elements, such as emitter to collector spacing, and in a large base region. Large active element spacing increases carrier transit time and carrier storage within the transistor thereby limiting the transistor's performance. Such lateral transistors generally have a cutoff frequency of less than seven gigahertz (GHz). Large base regions also increase the transistor's parasitic capacitance which further limits the transistor's performance.
Additionally, the transistor's base ohmic contact is typically positioned between the emitter and the collector ohmic contact thereby creating a large distance between the emitter and the collector. This large distance increases the transistor's collector resistance and limits the transistor's performance.
Accordingly, it is desirable to have a lateral bipolar transistor that occupies a small area, that has a high cutoff frequency (greater than seven GHz), and that has an emitter electrode positioned between the base and collector electrodes.